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?2007 silicon storage technology, inc. s71269-02-eol 5/07 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. combomemory is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. eol data sheet features: ? flash organization: 1m x16 ? 16 mbit: 12 mbit + 4 mbit ? concurrent operation ? read from or write to sram while erase/program flash ? sram organization: ? 2 mbit:128k x16 ? 4 mbit: 256k x16 ? single 2.7-3.3v read and write operations ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption: (typical values @ 5 mhz) ? active current: flash 10 ma (typical) sram 6 ma (typical) ? standby current: 10 a (typical) ? sector-erase capability ? uniform 2 kword sectors ? block-erase capability ? uniform 32 kword blocks ? read access time ? flash: 70 ns ?sram: 70 ns ? erase-suspend / erase-resume capabilities ? latched address and data ? fast erase and word-program (typical): ? sector-erase time: 18 ms ? block-erase time: 18 ms ? chip-erase time: 35 ms ? program time: 7 s ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bit ? data# polling ? cmos i/o compatibility ? jedec standard command set ? packages available ? 48-ball lbga (10mm x 12mm) ? all non-pb (lead-free) devices are rohs compliant product description the sst34hf162c/164c combomemory devices inte- grate a 1m x16 cmos flash memory bank with either 128k x16 or 256k x16 cmos sram memory bank in a multi- chip package (mcp). these devices are fabricated using sst?s proprietary, high-performance cmos superflash technology incorporating the split-gate cell design and thick-oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. the sst34hf162c/164c devices are ideal for applica- tions such as cellular phones, gps devices, pdas, and other portable electronic devices in a low power and small form factor system. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. the sst34hf162c/164c devices offer a guaranteed endurance of 10,000 cycles. data retention is rated at greater than 100 years. with high-performance program operations, the flash memory banks provide a typical program time of 7 sec. the entire flash memory bank can be erased and programmed word-by-word in 4 seconds (typically) for the sst34hf162c/164c, when using interface features such as toggle bit or data# polling to indicate the completion of program operation. to protect against inadvertent flash write, the sst34hf162c/164c devices contain on-chip hardware and software data pro- tection schemes. the flash and sram operate as two independent memory banks with respective bank enable signals. the memory bank selection is done by two bank enable signals. the sram bank enable signal, bes# , selects the sram bank. the flash memory bank enable signal, bef#, has to be used with software data protection (sdp) command sequence when controlling the erase and program opera- tions in the flash memory bank. the memory banks are superimposed in the same memory address space where they share common address lines, data lines, we# and oe# which minimize power consumption and area. see figure 1 for memory organization. designed, manufactured, and tested for applications requir- ing low power and small form factor, the sst34hf162c/ 164c are offered in both commercial and extended temper- atures and a small footprint package to meet board space constraint requirements. see figure 2 for pin assignments. 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c sst34hf162c16mb dual-bank flash + 2/4 mb sram mcp combomemory
2 eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c ?2007 silicon storage technology, inc. s71269-02-eol 5/07 device operation the sst34hf162c/164c use bes# and bef# to control operation of either the flash or the sram memory bank. when bef# is low, the flash bank is activated for read, program or erase operation. when bes# is low the sram is activated for r ead and write oper ation. bef# and bes# cannot be at low level at the same time. if all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. all address, data, and control lines are shared by flash and sram memory banks which minimi zes power consumption and loading. the device goes into standby when bef# and bes# bank enables are raised to v ihc (logic high) or when bef# is high. concurrent read/write operation the sst34hf162c/164c provide the unique benefit of being able to read from or write to sram, while simulta- neously erasing or programming the flash. this allows data alteration code to be executed from sram, while altering the data in flash. the following table lists all valid states. the device will ignore all sdp commands when an erase or program operation is in progress. note that product identification commands use sdp; therefore, these com- mands will also be ignored while an erase or program operation is in progress. flash read operation the read operation of the sst34hf162c/164c is con- trolled by bef# and oe#, both have to be low for the sys- tem to obtain data from the outputs. bef# is used for device selection. when bef# is high, the chip is dese- lected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either bef# or oe# is high. refer to the read cycle timing diagram for further details (figure 6). flash program operation these devices are programmed on a word-by-word basis. before programming, one must ensure that the sector which is being programmed is fully erased. the program operation is accomplished in three steps: 1. software data protection is initiated using the three-byte load sequence. 2. address and data are loaded. during the program operation, the addresses are latched on the fa lling edge of either bef# or we#, whichever occurs last. the data is latched on the rising edge of either bef# or we#, whichever occurs first. 3. the internal program oper ation is initiated after the rising edge of the fourth we# or bef#, which- ever occurs first. the program operation, once ini- tiated, will be completed typically within 7 s. see figures 7 and 8 for we# and bef# controlled pro- gram operation timing diagrams and figure 18 for flow- charts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal pro- gram operation, the host is free to perform additional tasks. any commands issued during an internal program opera- tion are ignored. flash sector- /block -erase operation these devices offer both sector-erase and block-erase operations. these operations allow the system to erase the devices on a sector-by-sector (or block-by-block) basis. the sector architecture is based on a uniform sector size of 2 kword. the block-erase mode is based on a uniform block size of 32 kword. the sector-erase operation is initi- ated by executing a six-byte command sequence with a sector-erase command (30h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by executing a six-byte command sequence with block-erase command (50h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. any commands issued during the block- or sector- erase operation are ignored except erase-suspend and erase-resume. see figures 12 and 13 for timing wave- forms. c oncurrent r ead /w rite s tate t able flash sram program/erase read program/erase write
eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c 3 ?2007 silicon storage technology, inc. s71269-02-eol 5/07 flash chip-erase operation the sst34hf162c/164c provide a chip-erase operation, which allows the user to erase all sectors/blocks to the ?1? state. this is useful when the device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or bef#, whichever occurs first. during the erase operation, the only valid read is toggle bits or data# polling. see table 5 for the command sequence, figure 11 for timing diagram, and figure 21 for the flowchart. any commands issued during the chip-erase operation are ignored. flash erase-suspend/-r esume operations the erase-suspend operation temporarily suspends a sector- or block-erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an erase operation. the operation is executed by issuing a one-byte command sequence with erase-suspend command (b0h). the device automatically enters read mode within 20 s after the erase-suspend command had been issued. valid data can be read from any sector or block that is not suspended from an erase operation. reading at address location within erase-suspended sect ors/blocks will output dq 2 tog- gling and dq 6 at ?1?. while in erase-suspend mode, a pro- gram operation is allowed except for the sector or block selected for erase-suspend. to resume sector-erase or block-erase operation which has been suspended, the system must issue an erase-resume command. the operation is executed by issuing a one-byte command sequence with erase resume command (30h) at any address in the one-byte sequence. flash write operati on status detection the sst34hf162c/164c provides two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling (dq 7 ) or toggle bit (dq 6 ) read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to pre- vent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. flash data# polling (dq 7 ) when the device is in an internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or bef#) pulse for program operation. for sector-, block-, or chip-erase, the data# polling is valid after the rising edge of sixth we# (or bef#) pulse. see figure 9 for data# poll- ing (dq 7 ) timing diagram and figure 19 for a flowchart. toggle bits (dq 6 and dq 2 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next opera- tion. the toggle bit is valid after the rising edge of the fourth we# (or bef#) pulse for program operations. for sector-, block-, or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# (or bef#) pulse. dq 6 will be set to ?1? if a read operation is attempted on an erase-sus- pended sector/block. if program operation is initiated in a sector/block not selected in erase-suspend mode, dq 6 will toggle. an additional toggle bit is available on dq 2 , which can be used in conjunction with dq 6 to check whether a particular sector is being actively erased or erase-suspended. table 1 shows detailed status bit information. the toggle bit (dq 2 ) is valid after the rising edge of the last we# (or bef#) pulse of a write operation. see figure 10 for toggle bit tim- ing diagram and figure 19 for a flowchart. table 1: w rite o peration s tatus status dq 7 dq 6 dq 2 normal operation standard program dq7# toggle no toggle standard erase 0 toggle toggle
4 eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c ?2007 silicon storage technology, inc. s71269-02-eol 5/07 note: dq 7, dq 6, and dq 2 require a valid address when reading status information. data protection the sst34hf162c/164c provide both hardware and soft- ware features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or bef# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, bef# high, or we# high will inhibit t he write operation. th is prevents inadvert- ent writes during power-up or power-down. software data protection (sdp) the sst34hf162c/164c provide the jedec standard software data protection scheme for all data alteration operations, i.e., program and erase. any program opera- tion requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. the sst34hf162c/164c are shipped with the software data protection permanently enabled. see table 5 for the specific software command codes. dur- ing sdp command sequence, invalid commands will abort the device to read mode within t rc. the contents of dq 15 - dq 8 are ?don?t care? during any sdp command sequence. product identification the product identification mode identifies the device as sst34hf162c or sst34hf164c and the manufacturer as sst. this mode may be accessed by software opera- tions only. the hardware device id read operation, which is typically used by programmers cannot be used on this device because of the shared lines between flash and sram in the multi-chip package. therefore, application of high voltage to pin a 9 may damage this device. users may use the software product identification operation to identify the part (i.e., using the device id) when using multiple man- ufacturers in the same socket. for details, see tables 4 and 5 for software operation, figure 14 for the software id entry and read timing diagram and figure 20 for the id entry command sequence flowchart. note: bk = bank address (a 19 -a 18 ) product identification mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. please note that the software id exit command is ignored during an internal program or erase operation. see table 5 for software command codes, fig- ure 15 for timing waveform and figure 20 for a flowchart. erase- suspend mode read from erase suspended sector/ block 1 1 toggle read from non-erase suspended sector/ block data data data program dq7# toggle no toggle t1.0 1269 table 1: w rite o peration s tatus status dq 7 dq 6 dq 2 table 2: p roduct i dentification address data manufacturer?s id bk0000h 00bfh device id sst34hf162c/164c bk0001h 734bh t2.1 1269
eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c 5 ?2007 silicon storage technology, inc. s71269-02-eol 5/07 sram operation with bes# low and bef# high, the sst34hf162c/164c operate as either 128k x16 or 256k x16 cmos sram, with fully static operation requiring no external clocks or tim- ing strobes. the sst34hf162c/164c sram is mapped into the first 128 kword address space. when bes# and bef# are high, all memory banks are deselected and the device enters standby. read and write cycle times are equal. the control signals ubs# and lbs# provide access to the upper data byte and lower data byte. see table 4 for sram read and write data byte control modes of opera- tion. sram read the sram read operation of the sst34hf162c/164c is controlled by oe# and bes#, both have to be low with we# high for the system to obtain data from the outputs. bes# is used for sram bank selection. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to the read cycle timing diagram, figure 3, for further details. sram write the sram write operation of the sst34hf162c/164c is controlled by we# and bes#, bot h have to be low for the system to write to the sram. during the word-write oper- ation, the addresses and data are referenced to the rising edge of either bes# or we# whichever occurs first. the write time is measured from the last falling edge of bes# or we# to the first rising edge of bes# or we#. refer to the write cycle timing diagrams, figures 4 and 5, for further details. 1269 b1.1 superflash memory (bank 1) i/o buffers superflash memory (bank 2) 2/4 mbit sram a msf 1 - a 0 a mss 2 - a 0 dq 15 - dq 0 control logic bef# lbs# ubs# we# oe# bes# address buffers address buffers notes: 1. a msf = most significant flash address a msf = a 19 for sst34hf162c/164c 2. a mss = most significant sram address a mss = a 16 for sst34hf162c and a 17 for sst34hf164c f unctional b lock d iagram
6 eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c ?2007 silicon storage technology, inc. s71269-02-eol 5/07 figure 1: d ual -b ank m emory o rganization fffffh f8000h block 31 f7fffh f0000h block 30 effffh e8000h block 29 e7fffh e0000h block 28 dffffh d8000h block 27 d7fffh d0000h block 26 cffffh c8000h block 25 c7fffh c0000h block 24 bank 2 bffffh b8000h block 23 b7fffh b0000h block 22 affffh a8000h block 21 a7fffh a0000h block 20 9ffffh 98000h block 19 97fffh 90000h block 18 8ffffh 88000h block 17 87fffh 80000h block 16 7ffffh 78000h block 15 77fffh 70000h block 14 6ffffh 68000h block 13 67fffh 60000h block 12 5ffffh 58000h block 11 57fffh 50000h block 10 4ffffh 48000h block 9 47fffh 40000h block 8 3ffffh 38000h block 7 37fffh 30000h block 6 2ffffh 28000h block 5 27fffh 20000h block 4 1ffffh 18000h block 3 17fffh 10000h block 2 0ffffh 08000h block 1 07fffh 02000h 01fffh 00000h block 0 bank 1 32 kword blocks; 2 kword sectors 1269 f01.0
eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c 7 ?2007 silicon storage technology, inc. s71269-02-eol 5/07 figure 2: p in a ssignments for 48- ball lbga (10 mm x 12 mm ) table 3: p in d escription symbol pin name functions a mss 1 to a 0 1. a ms = most significant address a ms = a 16 for sst34hf162c and a 17 for sst34hf164c address inputs to provide flash address, a 19 -a 0 . to provide sram address, a mss -a 0 dq 15 -dq 0 data inputs/outputs to output da ta during read cycles and receive input data during write cycles. data is internally latched during a flash erase/program cycle. the outputs are in tri-state wh en oe#, bes#, and bef# are high. bef# flash memory bank enable to activate the flash memory bank when bef# is low bes# sram memory bank enable to activate the sram memory bank when bes# is low oe# output enable to gate the data output buffers we# write enable to control the write operations ubs# upper byte control (sram) to enable dq 15 -dq 8 lbs# lower byte control (sram) to enable dq 7 -dq 0 v ss ground v dd f power supply (flash) 2.7-3.3v power supply to flash only v dd s power supply (sram) 2.7-3.3v power supply to sram only nc no connection unconnected pins t3.1 1269 bes# a10 oe# a11 a13 we# v ss dq5 dq7 a8 a17 v dds dq1 dq2 dq4 a5 ubs# a16 a1 a0 dq0 dq8 bef# v ss a2 a3 a6 dq3 dq10 dq9 a4 a7 a18 dq12 v ddf dq11 a19 nc nc a12 dq6 dq13 a9 a14 a15 lbs# dq15 dq14 a b c d e f g h sst34hf162c/164c 6 5 4 3 2 1 top view (balls facing down) 1269 48-lbga p1.1
8 eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c ?2007 silicon storage technology, inc. s71269-02-eol 5/07 table 4: o perational m odes s election for sram mode bef# 1 bes# 1,2 oe# 2 we# 2 lbs# 2 ubs# 2 dq 15-0 dq 15-8 full standby v ih v ih x x x x high-z high-z high-z xxxxx output disable v ih v il v ih v ih x x high-z high-z high-z v il xxv ih v ih v il v ih v ih v ih x x high-z high-z high-z x flash read v il v ih v il v ih xxd out d out dq 15-8 =high-z x flash write v il v ih v ih v il xxd in d in dq 15-8 =high-z x flash erase v il v ih v ih v il xx x x x x sram read v ih v il v il v ih v il v il d out d out d out v ih v il high-z d out d out v il v ih d out high-z high-z sram write v ih v il xv il v il v il d in d in d in v ih v il high-z d in d in v il v ih d in high-z high-z product identification 3 v il v ih v il v ih x x manufacturer?s id 4 device id 4 t4.1 1269 1. do not apply bef# = v il and bes# = v il at the same time 2. x can be v il or v ih, but no other value. 3. software mode only 4. with a 19 -a 18 = v il; sst manufacturer?s id = bfh, is read with a 0 =0, sst34hf162c/164c device id = 734bh, is read with a 0 =1
eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c 9 ?2007 silicon storage technology, inc. s71269-02-eol 5/07 table 5: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 program 555h aah 2aah 55h 555h a0h wa 3 data sector-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa x 4 30h block-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba x 4 50h chip-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h erase-suspend xxxxh b0h erase-resume xxxxh 30h software id entry 5 555h aah 2aah 55h bk x 6 555h 90h software id exit 555h aah 2aah 55h 555h f0h software id exit xxh f0h t5.0 1269 1. address format a 11- a 0 (hex), addresses a 19 -a 12 can be v il or v ih , but no other value, for the command sequence. 2. dq 15 -dq 8 can be v il or v ih , but no other value, for the command sequence 3. wa = program word address 4. sa x for sector-erase; uses a 19 -a 10 address lines ba x for block-erase; uses a 19 -a 15 address lines 5. the device does not remain in software product identification mode if powered down. 6. a 19 and a 18 = v il
10 eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c ?2007 silicon storage technology, inc. s71269-02-eol 5/07 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +125c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to v dd 1 +0.3v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd 1 +1.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. v dd = v ddf and v dds 2. excluding certain with-pb 32-plcc units, all packages are 260 c capable in both non-pb and with-pb solder versions. certain with-pb 32-plcc package types are capable of 240 c for 10 seconds; please consult the factory for the latest information. 3. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange range ambient temp v dd commercial 0c to +70c 2.7-3.3v extended -20c to +85c 2.7-3.3v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 16 and 17
eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c 11 ?2007 silicon storage technology, inc. s71269-02-eol 5/07 table 6: dc o perating c haracteristics (v dd = v ddf and v dds = 2.7-3.3v) symbol parameter limits test conditions min max units i dd 1 active v dd current address input = v ilt /v iht, at f=5 mhz, v dd =v dd max, all dqs open read oe#=v il , we#=v ih flash 15 ma bef#=v il , bes#=v ih sram 10 ma bef#=v ih , bes#=v il concurrent operation 45 ma bef#=v ih , bes#=v il write 2 we#=v il flash 40 ma bef#=v il , bes#=v ih , oe#=v ih sram 30 ma bef#=v ih , bes#=v il i sb standby v dd current 30 a v dd = v dd max, bef#=bes#=v ihc i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7 v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v olf flash output low voltage 0.2 v i ol =100 a, v dd =v dd min v ohf flash output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min v ols sram output low voltage 0.4 v iol =1 ma, v dd =v dd min v ohs sram output high voltage 2.2 v ioh =-500 a, v dd =v dd min t6.1 1269 1. see figure 16 2. i dd active while erase or program is in progress. table 7: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t7.0 1269 table 8: c apacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 20 pf c in 1 input capacitance v in = 0v 16 pf t8.0 1269 table 9: f lash r eliability c haracteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t9.0 1269
12 eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c ?2007 silicon storage technology, inc. s71269-02-eol 5/07 ac characteristics table 10: sram r ead c ycle t iming p arameters symbol parameter min max units t rcs read cycle time 70 ns t aas address access time 70 ns t bes bank enable access time 70 ns t oes output enable access time 35 ns t byes ubs#, lbs# access time 70 ns t blzs 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. bes# to active output 0 ns t olzs 1 output enable to active output 0 ns t bylzs 1 ubs#, lbs# to active output 0 ns t bhzs 1 bes# to high-z output 25 ns t ohzs 1 output disable to high-z output 25 ns t byhzs 1 ubs#, lbs# to high-z output 35 ns t ohs output hold from address change 10 ns t10.0 1269 table 11: sram w rite c ycle t iming p arameters symbol parameter min max units t wcs write cycle time 70 ns t bws bank enable to end-of-write 60 ns t aws address valid to end-of-write 60 ns t asts address set-up time 0 ns t wps write pulse width 60 ns t wrs write recovery time 0 ns t byws ubs#, lbs# to end-of-write 60 ns t odws output disable from we# low 30 ns t oews output enable from we# high 0 ns t dss data set-up time 30 ns t dhs data hold from write time 0 ns t11.0 1269
eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c 13 ?2007 silicon storage technology, inc. s71269-02-eol 5/07 table 12: f lash r ead c ycle t iming p arameters v dd = 2.7-3.3v symbol parameter min max units t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 35 ns t clz 1 bef# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 bef# high to high-z output 20 ns t ohz 1 oe# high to high-z output 20 ns t oh 1 output hold from address change 0 ns t12.0 1269 1. this parameter is measured only for init ial qualification and after the design or pr ocess change that could affect this param eter. table 13: f lash p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp program time 12 s t as address setup time 0 ns t ah address hold time 40 ns t cs we# and bef# setup time 0 ns t ch we# and bef# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp bef# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. we# pulse width high 30 ns t cph 1 bef# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t es erase-suspend latency 20 s t br 1 bus# recovery time 1s t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 50 ms t13.1 1269
14 eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c ?2007 silicon storage technology, inc. s71269-02-eol 5/07 figure 3: sram r ead c ycle t iming d iagram figure 4: sram w rite c ycle t iming d iagram (we# c ontrolled ) 1 addresses a mss-0 dq 15-0 ubs#, lbs# oe# bes# t rcs t aas t bes t oes t blzs t olzs t byes t bylzs t byhzs data valid t ohzs t bhzs t ohs 1269 f03.1 note: a mss = most significant address a mss = a 16 for sst34hf162c and a 17 sst34hf164c t aws addresses a mss 3 -0 bes# we# ubs#, lbs# t wps t wrs t wcs t asts t bws t byws t odws t oews t dss t dhs 1269 f04.1 note 2 note 2 dq 15-8, dq 7-0 valid data in note: 1. if oe# is high during the write cycle, the outputs will remain at high impedance. 2. if bes# goes low coincident with or after we# goes low, the output will remain at high impedance. if bes# goes high coincident with or before we# goes high, the output will remain at high impedance. because d in signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. a mss = most significant sram address a mss = a 16 for sst34hf162c and a 17 for sst34hf164c
eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c 15 ?2007 silicon storage technology, inc. s71269-02-eol 5/07 figure 5: sram w rite c ycle t iming d iagram (ubs#, lbs# c ontrolled ) 1 figure 6: f lash r ead c ycle t iming d iagram addresses a mss 3 -0 we# bes# t bws t aws t wcs t wps t wrs t asts t byws dq 15-8, dq 7-0 valid data in t dss t dhs ubs#, lbs# 1269 f05.1 note 2 note 2 note: 1. if oe# is high during the write cycle, t he outputs will remain at high impedance. 2. because d in signals may be in the output state at this time, i nput signals of reverse polarity must not be applied. 3. a mss = most significant sram address a mss = a 16 for sst34hf162c and a 17 for sst34hf164c 1269 f06.0 address a 19-0 dq 15-0 we# oe# bef# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz
16 eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c ?2007 silicon storage technology, inc. s71269-02-eol 5/07 figure 7: f lash we# c ontrolled p rogram c ycle t iming d iagram figure 8: f lash bef# c ontrolled p rogram c ycle t iming d iagram 1269 f07.0 address a 19-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs bef# 555 2aa 555 addr xxaa xx55 xxa0 data word (addr/data) oe# we# t bp note: x can be v il or v ih , but no other value. valid valid 1269 f08.0 address a 19-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# 555 2aa 555 addr xxaa xx55 xxa0 data word (addr/data) oe# bef# t bp note: x can be v il or v ih , but no other value.
eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c 17 ?2007 silicon storage technology, inc. s71269-02-eol 5/07 figure 9: f lash d ata # p olling t iming d iagram figure 10: f lash t oggle b it t iming d iagram 1269 f09.0 address a 19-0 dq 7 data data# data# data we# oe# bef# t oeh t oe t ce t oes 1269 f10.0 address a 19-0 dq 6 we# oe# bef# t oe t oeh t ce two read cycles with same outputs valid data t br
18 eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c ?2007 silicon storage technology, inc. s71269-02-eol 5/07 figure 11: f lash we# c ontrolled c hip -e rase t iming d iagram figure 12: f lash we# c ontrolled b lock -e rase t iming d iagram valid 1269 f11.0 address a 19-0 dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx10 xx55 xxaa xx80 xxaa 555 oe# bef# six-byte code for chip-erase t sce t wp note: this device also supports bef# controlled chip-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are met. (see table 13.) x can be v il or v ih, but no other value. 1269 f12.0 address a 19-0 dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# bef# six-byte code for block-erase t wp valid t be note: this device also supports bef# controlled block-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are met. (see table 13.) ba x = block address x can be v il or v ih, but no other value.
eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c 19 ?2007 silicon storage technology, inc. s71269-02-eol 5/07 figure 13: f lash we# c ontrolled s ector -e rase t iming d iagram figure 14: f lash s oftware id e ntry and r ead 1269 f13.0 address a 19-0 dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# bef# six-byte code for sector-erase t wp valid t se note: this device also supports bef# controlled sector-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are met. (see table 13.) sa x = sector address x can be v il or v ih, but no other value. 1269 f14.0 address a 14-0 t ida dq 15-0 we# 555 2aa 555 0000 0001 oe# bef# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: x can be v il or v ih, but no other value. device id - 734bh for sst34hf162c/164c
20 eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c ?2007 silicon storage technology, inc. s71269-02-eol 5/07 figure 15: f lash s oftware id e xit 1269 f15.0 address a 14-0 dq 15-0 t ida t wp t whp we# 555 2aa 555 three-byte sequence for software id exit and reset oe# bef# xxaa xx55 xxf0 note: x can be v il or v ih , but no other value
eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c 21 ?2007 silicon storage technology, inc. s71269-02-eol 5/07 figure 16: ac i nput /o utput r eference w aveforms figure 17: a t est l oad e xample 1269 f16.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1269 f17.0 to tester to dut c l
22 eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c ?2007 silicon storage technology, inc. s71269-02-eol 5/07 figure 18: p rogram a lgorithm 1269 f18.0 start load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxa0h address: 555h load address/data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but no other value.
eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c 23 ?2007 silicon storage technology, inc. s71269-02-eol 5/07 figure 19: w ait o ptions 1269 f19.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte/word data# polling program/erase completed program/erase completed read byte/word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
24 eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c ?2007 silicon storage technology, inc. s71269-02-eol 5/07 figure 20: s oftware p roduct id c ommand f lowcharts 1269 f20.0 load data: xxaah address: 555h software product id entry command sequence load data: xx55h address: 2aah load data: xx90h address: 555 wait t ida read software id load data: xxaah address: 555h software id exit command sequence load data: xx55h address: 2aah load data: xxf0h address: 555h wait t ida return to normal operation note: x can be v il or v ih, but no other value.
eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c 25 ?2007 silicon storage technology, inc. s71269-02-eol 5/07 figure 21: e rase c ommand s equence 1269 f21.0 load data: xxaah address: 555h chip-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx10h address: 555h load data: xxaah address: 555h wait t sce chip erased to ffffh load data: xxaah address: 555h sector-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx30h address: sa x load data: xxaah address: 555h wait t se sector erased to ffffh load data: xxaah address: 555h block-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx50h address: ba x load data: xxaah address: 555h wait t be block erased to ffffh note: x can be v il or v ih, but no other value.
26 eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c ?2007 silicon storage technology, inc. s71269-02-eol 5/07 product ordering information valid combinations for sst34hf162c sst34hf162c-70-4c-lbk sst34hf162c-70-4c-lbke SST34HF162C-70-4E-LBK SST34HF162C-70-4E-LBKe valid combinations for sst34hf164c sst34hf164c-70-4c-lbk sst34hf164c-70-4c-lbke sst34hf164c-70-4e-lbk sst34hf164c-70-4e-lbke note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. package attribute e 1 = non-pb package modifier k = 48 balls package type lb = lbga (10mm x 12mm x 1.4mm, 0.50mm ball size) temperature range c = commercial = 0c to +70c e = extended = -20c to +85c minimum endurance 4 =10,000 cycles read access speed 70 = 70 ns version c = sram sram density 2 = 2 mbit 4 = 4 mbit flash density 16 = 16 mbit voltage h = 2.7-3.3v product series 34 = dual-bank flash + sram combomemory 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. device speed suffix1 suffix2 sst34 h f162c - xxx -x x -xx x x
eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c 27 ?2007 silicon storage technology, inc. s71269-02-eol 5/07 packaging diagrams 48- ball l ow - profile b all g rid a rray (lbga) 10 mm x 12 mm sst p ackage c ode : lbk h g f e d c b a a b c d e f g h bottom view side view 6 5 4 3 2 1 seating plane 0.40 0.05 1.4 max 0.12 0.50 0.05 (48x) 1.0 5.0 1.0 7.0 48-lbga-lbk-10x12-500mic-2 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registere d. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.4 mm ( 0.05 mm) 6 5 4 3 2 1 1mm top view 10.00 0.20 12.00 0.20 a1 corner a1 corner
28 eol data sheet 16 mbit dual-bank flash + 2/4 mbit sram combomemory sst34hf162c / sst34hf164c ?2007 silicon storage technology, inc. s71269-02-eol 5/07 table 14: r evision h istory number description date 00 ? initial release aug 2004 01 ? adding 4 mbit sram parts and associated mpns ? removed pb-free mpns for sst34hf162c devices ? clarifed values for low power consumption on page 1 ? added 5 mhz specifications for active v dd current (i dd ) to table 6 on page 11 ? data sheet status changed to ?preliminary specifications? sep 2004 02 ? changed document status from ?preliminary specification? to ?data sheet? ? added rohs compliance information on page 1 and in the ?product ordering informa- tion? on page 26 ? added the solder reflow temperature to the ?absolute maximum stress ratings? on page 10. ? added pb-free mpns for all devices ? end-of-life data sheet for a ll valid combination in s71269 ? recommended replacement devices are sst34hf1641j found in s71336 may 2007 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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